The present invention relates to integrated circuit structures and fabrication methods.
In integrated circuit fabrication, a key area of concentration has been the fabrication of contacts. Contact holes must usually be etched down through a significant thickness of interlevel dielectric, and significant issues arise. Contact holes are normally etched simultaneously to the active region and to the poly-1 level (polycide gate conductor), and thus the interlevel dielectric will be much thicker over some locations, especially when the dielectric has been planarized. (Planarization of the interlevel dielectric is highly desirable to minimize topographic excursion, but means that in some locations the contact holes may tend to have a very large aspect ratio.) This means that a large amount of overetch must be tolerated at the contacts to the poly-1 level.
For best mechanical properties of the metal layer, it would be desirable to provide sloped contact hole sidewalls. This has commonly been done with oxide reflow techniques, in which a short high-temperature treatment of a doped silicate glass produces nicely rounded corners (due to the surface tension effects on the silicate glass layer when it softens). One problem with this approach is that the required time at high-temperature is increasingly undesirable as geometries shrink.
Another approach has been to use a fairly isotropic etch, to produce a contact hole with sloped sidewalls; but this consumes a large area. The lateral spread of the contact sidewalls means that a significant spacing must be required between contacts to active and the poly-1 layer, to prevent shorts to poly-1.
To achieve the best packing density, it would be desirable to use holes with nearly vertical sidewalls. However, such holes have a high aspect ratio (height/width ratio), and pose processing difficulties. Such geometries may present difficulties in completely filling the contact hole, or may cause an undesirable lack of planarity where the metal layer crosses over the hole. Such problems have been addressed by xe2x80x9cstud contactxe2x80x9d processes (where deposition and etchback of a highly conformal metal, such as W, precede deposition of a following metal such as Al:Cu). However, such processes add expense and complexity, and are more often used for vias than contacts.
One proposed method uses a second poly as the xe2x80x9clanding padsxe2x80x9d for bitline contacts in the matrix. In this way, the wordlines are protected thereby allowing for zero contact-to-gate spacing. The drawback is that this method cannot be used in the periphery due to contact resistance problems which result in slower operation of the device.
Another method uses a silicon nitride deposition on top of the polycide prior to pattern and etch. (See Singer, xe2x80x9cA New Technology for Oxide Contact and Via Etchxe2x80x9d, SEMICONDUCTOR INTERNATIONAL, August 1993, p.36, which is hereby incorporated by reference.) Through the use of highly selective nitride to oxide etch selectivities, this will reduce the possibility of the contact touching the top of the polycide; however, it can still make contact along the sidewall due to the removal of the oxide spacer. Additionally, this does not address the problem of overetching the field oxide during the spacer etch.
Still another proposed method uses an Al2O3 etch-stop layer to achieve a zero-margin contact process. (See Fukase et al., xe2x80x9cA Margin-Free Contact Process Using an Al2O3 Etch-Stop Layer for High-Density Devices,xe2x80x9d 1992 IEDM PROCEEDINGS 33.3, which is hereby incorporated by reference.).
The present application sets forth a new approach to contact formation, using a combination of isotropic and anisotropic etch steps to produce a contact profile which has steep sidewalls at its bottom portion and sloped sidewalls at its top portion. This approach recognizes that the constraints on the top part of the contact hole are different from those on the bottom part of the contact hole, and accordingly obtains the advantages of both steep-sidewall and sloped-sidewall geometries:
at the lower level, the contact occupies only a small area, and hence it is not necessary to impose large minimum spacing from the contact to adjacent polysilicon;
at the upper level, the contact has nicely sloped sidewalls, so that problems of metal voids and cracking, and electromigration are greatly simplified.
The present application also describes a new method of forming sub-micron contact utilizing Si3N4 (or other dielectric film with good etch selectivity to oxide film) as an etch stop for a WET oxide etch. After the wet etch, an anisotropic plasma etch is used to cut a substantially vertical contact hole through the nitride and underlying layers. Thus, the resulting contact hole has a xe2x80x9cYxe2x80x9d-shaped profile.
Since the lower silicate glass layer and the nitride layer are not highly planarized, they provide area-efficient protection of the devices from any lateral encroachments which might occur during contact etching. Most of the planarization is performed in the upper silicate glass layer.
Thus, the lower silicate glass layer and the nitride layer provide self-aligned protection for the gate layer. This protection ensures that no possible combination of geometries will permit the contact etch to create a short circuit to the gate layer.
According to a disclosed class of innovative embodiments, there is provided: A fabrication method, comprising the steps of: providing a partially fabricated integrated circuit structure which includes transistors; forming an interlevel dielectric structure over said transistors, said interlevel dielectric including at least a lower layer having a first composition, a middle layer having a second composition which is different from said first composition, and an upper layer having a third composition which is different from said second composition; etching through said upper layer, using a relatively isotropic etch process which is selective to said second composition; etching through said middle and lower layers, using a relatively anisotropic etch process, to expose portions of said transistors; and depositing and patterning a thin-film conductor layer, to interconnect said transistors in a desired pattern.
According to another disclosed class of innovative embodiments, there is provided: A fabrication method, comprising the steps of: providing a partially fabricated integrated circuit structure which includes transistors; forming an interlevel dielectric structure over said transistors, said interlevel dielectric including at least a lower layer consisting predominantly of silicate glass, a middle layer consisting predominantly of silicon nitride, and an upper layer consisting predominantly of doped silicate glass; etching through said upper layer, using a relatively isotropic etch process which is selective to said second composition; etching through said middle and lower layers, using a relatively anisotropic etch process, to expose portions of said transistors; and depositing and patterning a thin-film conductor layer, to interconnect said transistors in a desired pattern.
According to another disclosed class of innovative embodiments, there is provided: A method, comprising the steps of: providing a partially fabricated integrated circuit structure which includes transistors; forming an interlevel dielectric structure over said transistors, said interlevel dielectric including at least a lower layer having a first composition, a middle layer having a second composition which is different from said first composition, and an upper layer having a third composition which is different from said second composition; etching through said upper layer, using a wet etch process which is selective to said second composition; etching through said middle and lower layers, using a relatively anisotropic plasma etch process, to expose portions of said transistors; and depositing and patterning a thin-film conductor layer, to interconnect said transistors in a desired pattern.
According to another disclosed class of innovative embodiments, there is provided: A method, comprising the steps of: providing a partially fabricated integrated circuit structure which includes transistors; forming an interlevel dielectric structure over said transistors, said interlevel dielectric including at least a lower layer having a first composition, a middle layer having a second composition which is different from said first composition, and an upper layer having a third composition which is different from said second composition; etching through said upper layer, using a wet etch process which is selective to said second composition; etching through said middle and lower layers, using a relatively anisotropic plasma etch process, to expose portions of said transistors; and depositing and patterning a thin-film metal layer, without any intermediate etchback steps, to interconnect said transistors in a desired pattern.
According to another disclosed class of innovative embodiments, there is provided: An integrated circuit, comprising: a substrate having transistors formed at one surface thereof; an interlevel dielectric overlying said transistors, and having at least upper, middle, and lower layers, said middle layer having a different composition from said upper layer and from said lower layer, and having contact holes therein extending vertically therethrough, said contact holes having vertical sidewalls in said lower layer and sloped sidewalls in said upper layer; and a patterned thin-film metal layer extending through said contact holes to interconnect said transistors in a desired electrical configuration.